The present invention relates generally to a method of processing semiconductor wafers, and more particularly to a method of processing double side polished wafers that contain external gettering sites.
Semiconductor integrated circuits are manufactured by combining connected circuit elements, such as transistors, diodes, resistors, and capacitors, within a continuous substrate wafer, such as a silicon wafer. Manufacturers of integrated circuits are continually trying to improve performance and reduce the size of semiconductors in order to reduce cost of manufacture, with line widths reaching 0.13 microns or smaller. This improvement naturally requires improvements in the quality of the wafers used as the substrate for such circuitry. Some of the factors that impact the ability to reduce the size of the integrated circuit include flatness of the substrate wafer and contamination levels both within the wafer bulk and on the surfaces of the wafer.
Semiconductor wafers are manufactured typically by growing a monocrystalline ingot using Float Zone, Ribbon Growth, or more commonly, a Czochralski technique. The ingot is then sliced into individual wafers using an inner diameter saw where wafers are sliced individually from the ingot, or a wire saw wherein the entire ingot is sliced into wafers simultaneously. The wafers are then subjected to an edge profiling process to round the edges and remove stress points. A wafer thinning step is then employed, such as lapping or surface grinding, to both remove slicing damage from the surfaces of the wafer and to make the opposing surfaces as flat and coplanar as possible. Because much of the equipment used to slice and shape the surfaces of the wafer are metal, and because metallic contaminants negatively effect the quality of an integrated circuit, the wafer is then subjected to a chemical etching, which removes metal ions from the surfaces of the wafer and assists in removing the finer surface damage caused by the lapping or surface grinding steps. Historically, one side of the wafer has then been polished to a mirror-like finish to provide a smooth surface for manufacture of the integrated circuit. This surface that will be used for manufacture of the integrated circuit is typically called the xe2x80x9cfront sidexe2x80x9d of the wafer, with the opposing side being called the xe2x80x9cback sidexe2x80x9d of the wafer.
Because small amounts of metallic impurities are grown into the crystal originally, an extrinsic gettering method has often been used on the back side of the wafer to gather and trap these metallic impurities. This extrinsic gettering has typically been accomplished by introducing small amounts of damage to the back side of the wafer by various techniques such as a wet sand blast. The wafer is then heat treated to allow the metallic impurities to diffuse through the wafer bulk to the damaged area on the back side of the wafer, where the impurities gather and are trapped. Another common technique for this extrinsic gettering is to deposit a thin polycrystalline film on the back of the wafer by chemical vapor deposition (CVD), which is performed at elevated temperatures, and assists the impurities in diffusing through the wafer bulk to the grain boundaries of the polycrystalline silicon, where they are gettered and trapped. Unfortunately, since there is damage on the back side of the wafer, the damage also acts as a trap for particles and other contaminants in the ambient surroundings of the wafer. These particles may become dislodged at inopportune times, and cause failure or decreased yield in the manufacture of the integrated circuit.
One of the methods utilized to improve flatness of the substrate wafer and simultaneously improve the surface contamination levels is polishing both sides of the substrate wafer, know as double side polishing, or DSP. DSP can be performed by polishing both sides of the wafer simultaneously, or by polishing one side at a time. However, a wafer polished on both sides loses extrinsic gettering capabilities. As such, efforts have been made to perform partial backside polish, where some of the damage, or surface roughness, is removed. This offers some extrinsic gettering abilities, but sacrifices some of the benefits associated with double side polishing in that particles can still be trapped in the surface roughness. Conversely, if both sides of the substrate wafer are polished to a complete polish, sometimes known as a xe2x80x9cmirror polishxe2x80x9d, the surface roughness on both sides is reduced to a few Angstroms or less. This complete polished surface is fine enough to prevent particle trapping, but is so fine that little or no extrinsic gettering is available.
Therefore, a need exists for a double side polished wafer where a complete polish is possible on both sides of the wafer, with the wafer still having extrinsic gettering capabilities.
The present invention relates to a semiconductor substrate wafer which has been polished on both sides to a complete or mirror polish but provides extrinsic gettering on the back side of the wafer, and a method for manufacturing such a wafer. In the present invention, a semiconductor substrate wafer is prepared by slicing an ingot into wafers. This slicing can be accomplished by either an inner-diameter saw where wafers are sliced sequentially, or by a wire saw, wherein the entire ingot is sliced into multiple wafers simultaneously. The wafer is then subjected to an edge grinding process, where the periphery of the wafer is chamfered to increase strength and remove sharp edges that can easily be chipped or broken. Lapping or surface grinding both surfaces of the wafer to remove slicing damage and to make the front and back surfaces both flat and parallel to each other is next performed on the wafer. After lapping or surface grinding, the wafer is chemically etched. Common etchants can be either an acid mixture, such as a mixture of Nitric, Acetic, and Hydroflouric acids, or a caustic mixture, such as Sodium Hydroxide. A sequential etch where -first one solution and then the other solution is utilized may also be employed. Etching is performed to remove the damage caused by lapping or surface grinding, to remove metals contamination, and to improve brightness on the wafer surfaces. A wafer identification process, such as a laser marking process, may be employed if desired, said process being inserted either immediately before or after the lapping or surface grinding process.
The back side of the wafer is then polished to a complete, or mirror polish. In this case, a complete or mirror polish on the back side of the wafer as a polish that is no more than 2 times the surface roughness or other measurement characteristics as that of the polished front side. For example, if the front side of the wafer is polished to a surface roughness of 5 xc3x85, the back side would have a surface roughness of no more than 10 xc3x85.
After the back side of the wafer is polished, a thin polysilicon layer is deposited on the wafer, and the wafer is then subjected to an oxidation step. The oxidation step consumes the polysilicon layer and forms stacking faults at the back surface of the wafer. Once the stacking faults are formed, the oxide layer is then stripped from both sides of the wafer, and the front side of the wafer is subjected to a complete polish. This process is useful for all wafer diameters.